New PDF release: Digital Design and Fabrication

By Vojin Oklobdzija

ISBN-10: 0849386020

ISBN-13: 9780849386022

ISBN-10: 0849386047

ISBN-13: 9780849386046

Based on large progress and new applied sciences within the semiconductor undefined, this quantity is prepared into 5, information-rich sections. electronic layout and Fabrication surveys the most recent advances in machine structure and layout in addition to the applied sciences used to fabricate and try out them. that includes contributions from prime specialists, the publication additionally encompasses a new part on reminiscence and garage as well as a brand new bankruptcy on nonvolatile reminiscence applied sciences. ? constructing complicated ideas, this sharply centred booklet— Describes new applied sciences that experience turn into riding components for the digital undefined contains new info on semiconductor reminiscence circuits, whose improvement most sensible illustrates the exceptional growth encountered through the fabrication and know-how zone includes a part devoted to matters concerning procedure energy intake Describes reliability and testability of computers Pinpoints developments and cutting-edge advances in fabrication and CMOS applied sciences Describes functionality evaluate measures, that are the base line from the user’s perspective Discusses layout strategies used to create sleek desktops, together with high-speed computing device mathematics and high-frequency layout, timing and clocking, and PLL and DLL layout

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Example text

For NiSi salicide, there was no narrow line effect—increase in the sheet resistance in narrow silicide line—and bridging failure by the formation of silicide path on the gate sidewall between the gate and S=D. NiSi-contact resistances to both nþ and pþ Si are small. These properties Epi Channel MOSFETs June 1993 are suitable for reducing the source, drain, and gate Epitaxial channel resistance for sub-50 nm MOSFETs. Channel ion implantation The previous discussion provides examples of possible solutions, which the authors found in the 1990s for sub50 nm gate length generation.

J. P. Liu, P. Gaworzewski, E. Bugiel, and P. Zaumseil, ‘‘High-k gate dielectrics with ultralow leakage current based on praseodymium oxide,’’ IEDM Tech. , pp. 653–656, 2000. 43. A. P. Gusev, E. Cartier, H. Okorn-Schmidt, K. A. Gribelyuk, A. Mocuta, A. Ajmera, M. Copel, S. Guha, N. Bojarczuk, A. Callegari, C. D’Emic, P. Kozlowski, K. J. C. Jamison, J. Brown, and R. Arndt, ‘‘80 nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications,’’ IEDM Tech. , pp. 223–226, 2000.

Nagisetty, P. Packan, J. Sebastian, M. Taylor, J. Tsai, S. Tyagi, S. Yang, and M. Bohr, ‘‘100 nm gate length high performance=low power CMOS transistor structure,’’ IEDM Tech. , pp. 415–418, December, 1999. 18. G. I. K. Bourdelle, J. Garno, A. Ghetti, H. Gossmann, M. Green, G. Forsyth, Y. Kim, R. Kleiman, F. Klemens, A. Komblit, C. Lochstampfor, W. Mansfield, S. Moccio, T. M. Tennant, W. Timp, and R. Tung, ‘‘The ballistic nano-transistor,’’ IEDM Tech. , pp. 55–58, December, 1999. 19. H. S. Momose, ‘‘Ultra-thin gate oxide—performance and reliability,’’ IEDM Tech.

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Digital Design and Fabrication by Vojin Oklobdzija


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